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    • 专利摘要:
    Memory device with a set of memory cells (C1m, C2m, C3m, C4m, C5m, C6m, C7m, C8m, Ci, Ck) having a first inverter and a second inverter each connected to a supply line from a first supply line and a second supply line, the memory device being provided with a circuit element configured for: - during a start-up phase following a power-up, apply a first pair of potentials (VDD, GND), respectively on the first supply line (LVDD1) and the second supply line (LVDD2), in order to preload logical data to certain cells according to the manner in which these cells are respectively connected to said supply lines, - then during a second phase apply a second pair of potentials (VDD, VDD) respectively on said first supply line (LVDD1) and the second supply line (LVDD2), so as to supply symmetrically the inverters of each cell.
    公开号:FR3083911A1
    申请号:FR1856515
    申请日:2018-07-13
    公开日:2020-01-17
    发明作者:Adam Makosiej；David CORIAT
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    SRAM / ROM MEMORY RECONFIGURABLE BY CONNECTIONS TO POWER SUPPLIES DESCRIPTION
    TECHNICAL AREA AND PRIOR ART
    The invention relates to the field of static random access memories SRAM (SRAM for “Static Random Access Memory”), and relates more particularly to that of memories, provided with cells having a structure of SRAM, and also capable of integrating a function. ROM memory for (“Read-Only Memory”).
    In this area, the document US Pat. No. 5,365 ° 475 presents a memory cell having a SRAM structure with 6 transistors which, using an additional supply line and an additional ground line, can be used, by means of a fixed polarization of its transistors, like a ROM memory cell. The behavior in conventional ROM or SRAM mode of the cell is frozen, during the manufacture of the memory, by choosing the way in which the latter is connected to the supply lines and ground lines.
    Furthermore, to carry out its startup, a digital system uses data which are typically stored in a space of a ROM memory. Once this startup has been performed, during system operation, this ROM memory space is generally unused.
    The document “Area Efficient ROM-Embedded SRAM Cache”, by Dongsoo Lee et al., IEEE Transactions on VLSI systems, vol. 21, n ° 9, 2013 presents a memory formed from SRAM cells capable of operating according to a conventional SRAM memory mode during which the cells are accessible in read and write, and also capable of adopting another mode of operation in which they are read-only. The transition from one mode to another is carried out using an additional word line, the polarization of which is modified. This additional word line requires a substantial modification of the control circuits external to the cell matrix, and in particular of the word line driver and of the associated control logic.
    The problem therefore arises of finding a new memory device endowed with a ROM memory functionality and which is improved with respect to the drawbacks mentioned above, in particular which is reconfigurable or reusable, with a reduced bulk, and does not require substantial modification of external control circuits.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of examples of embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which:
    - Figures 1A-1B give an equivalent electrical diagram of a first memory cell belonging to a memory plane of a memory device according to the invention during two consecutive phases during which, by means of power supply lines for inverters and signals applied to these lines, logic information is preloaded in the first cell before rendering it a SRAM cell functionality accessible in read and write;
    FIG. 2 gives an example of a timing diagram of voltages capable of being applied to a first supply line and to a second supply line of the inverters of a memory cell during the two aforementioned consecutive phases;
    - Figures 3A-3B give an equivalent electrical diagram of another memory cell of the same device as the first and during the same two consecutive phases, this other cell having a connection to the supply lines of the inverters different from that of the first in order to preload logical information different from that preloaded in the first cell;
    - Figures 4, 5, 6 respectively give a first example, a second example, and a third embodiment of a circuit for applying a sequence of supply voltages to the first and second supply lines during the two aforementioned phases;
    - Figures 7A-7D serve to illustrate possible configurations of connections of a cell to the first supply line and to the second supply line;
    FIGS. 8A-8B give an example of a particular arrangement of memory cells in a column of a memory device in which every second cell of the column is preloadable so as to be readable like a ROM, then rewritable thereafter, while the other cells adopt conventional SRAM cell operation;
    FIGS. 9A-9B serve to illustrate an example of correspondence between a set of virtual addresses relating to a RAM memory, and a physical memory such as implemented according to an embodiment of the present invention comprising a sector of SRAM cells and a sector of SRAM cells, some of which are preloadable such as ROM memory cells;
    - Figures 10A-10C give different embodiments of a virtual memory address conversion module physical address for a memory device as implemented according to an embodiment of the present invention;
    Identical, similar or equivalent parts of the different figures have the same reference numerals so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
    STATEMENT OF THE INVENTION
    One embodiment of the present invention provides a memory device provided with:
    - a set of memory cells each memory cell of said set comprising:
    - a first node and a second node,
    - a first inverter and a second inverter cross-connected between said first node and said second node, the memory device further comprising:
    a first supply line connected to one of a first transistor of the first inverter and a second transistor of the second inverter,
    a second supply line connected to the other among said first transistor of the first inverter and said second transistor of the second inverter, the second supply line being distinct from the first supply line, the memory device being provided with a circuit configured for, during an initialization sequence:
    - during a first phase, apply a first pair of potentials, respectively to the first supply line and the second supply line, so as to impose on cells of said set, preload logic data on which the respective values depend of the supply line among said first and second supply lines to which its first transistor and its second transistor are respectively connected, then
    - during a second phase, apply a second pair of potentials respectively to said first supply line and the second supply line, the second pair of potentials being different from the first pair of potentials and provided so as to maintain these data preload logic and make the cells of said set accessible in read and write.
    The cells of said set are thus automatically preloaded by the sequence of potentials applied to the first supply line and the second supply line, according to respective values which depend on their respective arrangements vis-à-vis the first supply line and second supply line.
    The arrangement of each cell with respect to the supply lines and the preloaded data value associated with this arrangement are typically determined during the design of the device. This preload data can thus constitute data from a ROM memory or a ROM memory code which is automatically imposed on the set of cells following the initialization sequence.
    Thus, without necessarily having to modify the internal line decoder of the memory and while limiting the space requirement, this circuit makes it possible to use the cells of said assembly as ROM memory cells, then, once data or data from the memory ROMs are read, use these cells as cells of a SRAM memory operating in a conventional manner.
    Advantageously, the initialization sequence can be consecutive to a powering up of a system in which the memory device is integrated.
    Thus, the circuit making it possible to establish the initialization sequence defined above can be configured to:
    during the first phase, apply the first pair of potentials by energizing the first supply line without supplying the second supply line, then, after a predetermined delay relative to the start of the first phase,
    - according to the second phase, apply the second pair of potentials by keeping the first supply line energized while energizing the second supply line, the first supply line and the second supply line can then be put to the same potential.
    According to a first possibility of implementation, such a circuit can include:
    a first portion of the circuit and a second portion of the circuit each receiving a supply voltage VDD,
    a first switching element, typically provided with at least one transistor, between the first portion and the first supply line, capable of alternately disconnecting and then connecting the first portion of the circuit to the first supply line following a change of 'state of a first control signal,
    a second switch element, typically provided with at least one other transistor, arranged between the second portion and the second supply line, capable of alternately disconnecting and then connecting the second portion of the circuit to the second supply line following a change of state of a second control signal, the change of state of the second control signal being delayed, according to said predetermined delay, with respect to the change of state of the first control signal.
    According to a second possibility of implementation, such a circuit can include:
    a first portion and a second portion each receiving a supply voltage VDD,
    - at least a first buffer circuit between the first portion and the first supply line,
    - At least a second buffer circuit between the second portion and the second supply line, said first buffer having a gain in current different from that of the second buffer.
    According to a third possibility of implementation, such a circuit can include:
    a first portion connected to the first supply line and to a node receiving a supply voltage VDD,
    - A second portion connected to said node, at least one delay cell being disposed between the second portion and the second supply line.
    Typically, the device comprises at least a first cell of said assembly having its first inverter connected to the first supply line and its second inverter connected to the second supply line and at least one other cell having its first inverter connected to the second supply line and its first inverter connected to the second supply line. In this case, this other cell stores data of value complementary to that stored by the first cell.
    The memory device can also include another cell having its two inverters connected to the same supply line given among said first supply line and second supply line. In this case, this other cell is polarized like a conventional SRAM cell immediately after the initialization sequence.
    One embodiment thus provides that the set of cells may include a second cell adjacent to the first cell and having its two inverters connected to the same given supply line among said first supply line and second supply line, the first cell and the second cell sharing a first common connection area connected to said given supply line. Such a common connection area makes it possible to reduce the bulk and can make it possible to make the various connections to the supply lines in a standard manufacturing technology.
    The set of cells can include a third cell located on a same column of cells as the first cell and the second cell so that the second cell is located between the first cell and the third cell, the third cell having one of its inverters connected to the first supply line and another of its inverters connected to the second supply line. Thus, the third cell is preloadable and can be used as a ROM memory cell.
    The third cell may be a cell adjacent to the second cell and share with the second cell a second common connection area, the second common connection area being connected to the first supply line when the first common connection area is connected to the first supply line or the second common connection area being connected to the second supply line when the first common connection area is connected to the second supply line.
    The cell assembly can be provided with at least a fourth cell arranged on a same column of cells as the first cell, the second cell and the third cell, the fourth cell having inverters connected to the second supply line.
    Advantageously, the memory device according to the invention can be provided with a first sector comprising said set of cells, in other words with cells which can operate as preloadable RAM cells and which can thus adopt the operating mode described above, and a second sector comprising memory cells used only as conventional SRAM cells.
    This second sector can be formed of SRAM cells provided with inverters connected to the same supply line among the supply lines LVDD1, LVDD2 or receiving the same supply potential during the first phase and during the second phase, or connected arbitrarily to preload arbitrary values which are not used when reading the ROM memory.
    Advantageously, said set of cells belongs to a matrix plane arranged in columns and in horizontal rows (alternately even and odd) of cells. The memory device is then advantageously configured so that one horizontal row out of two of cells constitutes a ROM memory following the initialization phase described above.
    In this case, when the first cell belongs to an odd horizontal row of cells, other cells of said set belonging to other odd rows are also preloadable.
    As a variant, when the first memory cell belongs to a paired horizontal row of cells, other cells of said set belonging to other even rows are also preloadable.
    To allow access to cells successively serving as ROM memory cells and then RAM memory cells, the memory device can further comprise a module for converting virtual memory addresses to physical memory addresses.
    This conversion module can be fitted with an offset module configured for:
    when accessing a preloaded cell, typically when restarting a circuit, detecting a signal indicating a first type of memory access (ROM) relating to access to memory cells accessible in read-only mode of said together, and accordingly apply a first type of shift operation to a virtual address in order to produce a physical address, then, during an SRAM access, typically after restarting or booting the system, detecting an indicator signal of a second type of memory access (RAM), relating to access to memory cells accessible in read and write of said set, and to apply accordingly a second type of shift operation to a virtual address in order to produce a physical address, the second type of shift operation being different from said first type of shift operation.
    The first type of shift operation can be provided so as to restrict access only to even horizontal rows among said horizontal rows of said set of cells or to restrict access only to odd horizontal rows among said horizontal rows of said set cells, while the second type of shift operation is capable of providing access to all of the horizontal rows of said set of cells.
    The conversion module can include a decoder configured to:
    - from a virtual address, produce the signal indicating a first type of relative memory access or a signal indicating a second type of memory access,
    - transmit this virtual address to the shift module.
    Provision may be made to integrate the set of cells, said shift module, and advantageously the decoder on the same support.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    We now refer to FIGS. 1A-1B, and 2 which serve to illustrate different phases of an initialization sequence of a memory cell C, elementary of a memory device as implemented according to an embodiment of the present invention. During this initialization sequence, logical information is preloaded and imposed on this cell C i. This information or logical data corresponds to a ROM memory data.
    The memory cell C, represented has a memory structure SRAM and is thus provided with two nodes T and F, provided to store logical information in the form of a first logical datum, and of a second logical datum complementary to the first datum . Maintaining the logical data in the nodes T, F is ensured by transistors TL T , TL F , TD T , TD F forming inverters looped on themselves, that is to say mounted in antiparallel or head to tail. Thus, a first inverter has an input connected to the first node and to an output of another inverter, the first inverter further having an output connected to the second node and to an input of the other inverter. This other inverter therefore has an input connected to the second node and an output connected to the first node.
    In the illustrated embodiment, the SRAM cell has a structure of the type commonly called “6T” and thus comprises 6 transistors, the two inverters then being produced by two charge transistors TL T , TL F , in this example of PMOS type , and also called “pull up”, and two conduction transistors, in this example of the NMOS type and also called “pull down”. The TL T , TD T transistors form one side of the cell, while the TL F , TD F transistors here form another side of the cell.
    Cell C is also provided with two access transistors TA T and TA F having a conventional arrangement. The access transistors TA T and TA F are respectively connected to so-called bit lines BL T and BL F generally shared by the SRAM cells of the same column of cells of a matrix plane formed of cells arranged in lines (rows horizontal) and in columns (vertical rows). Access to the nodes T and F is controlled by a word line WL generally shared by or the SRAM cells of the same line (horizontal row) of cells of the matrix plane. The access transistors TA T and TA F are thus provided to allow access or block access to the first node T and to the second node F respectively.
    In the illustrated embodiment, cell Ci has the particularity of having its first inverter and the second inverter which are not connected to the same supply line but connected respectively to a first supply line LVDD1 and to a second LVDD2 supply line separate from the first LVDD1 supply line. The supply lines LVDD1, LVDD2 may be put at different potentials from each other.
    In this particular embodiment, a first load transistor TL T here of PMOS type is connected to the first supply line LVDD1 while a second load transistor TL F is connected to the second supply line LVDD2, these transistors TL t , TL f can thus be polarized differently from one another, while the conduction transistors TD T , TD F , in particular of the NMOS type are in turn connected to the same LGND line , which can be set for example to a reference or GND ground potential.
    During a first phase Φ1 of an initialization sequence (Figure IA, and timing diagram of Figure 2), a first potential VDDlhigh, in this example equal to the supply voltage VDD, is applied to the first supply line LVDD1, while a second potential VDD2low different from the first potential, in this example equal to the ground potential GND, is applied to the second supply line LVDD2.
    The application of this pair of different potentials causes an asymmetric polarization of the load transistors of the inverters relative to each other. An asymmetrical or unbalanced supply on one side of the cell compared to the other makes it possible to impose on the nodes T, F preload values. The preloaded logic data is then imposed on the nodes T, F without making use of the bit lines which are usually used to write or read data when the cell C, finds itself in its normal operating mode, in other words that of conventional SRAM.
    The cell Ci is initialized during the first phase Φ1 as a ROM memory cell. The pair of potentials VDD, GND applied respectively to the first line LVDD1 and LVDD2 causes in this example a preload of the two nodes T and F, respectively at a logic level '1' and at the complementary logic level '0'. Logical information is thus preloaded in cell C ,, and its value depends on the manner in which cell Ci is connected to the supply lines LVDD1, LVDD2 and the pair of potentials applied to them during the first phase .
    Advantageously, the first phase during which cell C, is initialized and preloaded, is consecutive to a powering up of the memory device (powering up occurring in the example of timing diagram given in FIG. 3 at an instant t 0 ).
    In this case, if we refer to the example given above, powering up the memory device causes the supply voltage VDD of the first supply line LVDD1 to be energized while the second supply line LVDD2 is not supplied and left at GND ground potential during the first phase.
    According to a second phase Φ2 (FIG. 1B and timing diagram of FIG. 2), a symmetrical supply of the load transistors of the inverters is established. For this, the pair of potentials applied respectively to the first supply line LVDD1 and to the second supply line LVDD2 is modified.
    For this second phase, a potential VDDlhigh is maintained for example equal to the supply potential VDD on the first line LVDD1 while on the second supply line LVDD2, a higher potential VDD2high than that provided for the first phase is applied. The second supply line LVDD2 is for example set to the supply potential VDD, so that the load transistors TL T and TL f have their sources at the same potential, as is the case for a conventional SRAM cell.
    Thus, during the second phase, the cell Ci maintains the preloaded logic data imposed during the first phase while becoming, by means of a balanced or symmetrical supply between the two sides of the cell, equivalent to a SRAM cell. then accessible in reading and writing.
    When the first phase Φ1 results from a powering up of the memory device, the second phase lors2 during which the cell Ci becomes accessible in reading and writing can be implemented by a delayed powering up of the second line of LVDD2 supply according to a predetermined delay Tdeiay.
    Examples of embodiment of a circuit making it possible to apply the potentials to the lines LVDD1, LVDD2 during the different phases of the abovementioned initialization sequence, and in particular to allow such a delayed power-up, will be given later.
    FIGS. 3A-3B serve to illustrate the operation of another elementary cell Ck of the memory device during the same first phase Φ1 and second phase Φ2 of the initialization sequence.
    This other cell Ck belonging to the same matrix arrangement as cell C ,, and in particular to the same column of cells as cell Ci, differs from cell Ci by its connection to the supply lines LVDD1 and LVDD2.
    In this example, the first inverter and the second inverter of the cell Ck, are respectively connected this time to the second supply line LVDD2 and to the first supply line LVDD1. Thus, the source of the first load transistor TL T is connected to the second supply line LVDD2 while the source of the load transistor TL F is connected to the first supply line LVDD1.
    If we follow the example of polarization of the supply lines LVDD1, LVDD2 previously described for the first phase, potentials VDD and GND are applied respectively to the first line LVDD1 and the second supply line LVDD2. This entails putting the two storage nodes T and F of the cell Ck, respectively at a logical level '0' and at the logical level '1' fixed. During the first phase (FIG. 3A), the cell Ck is thus also preloaded like a ROM memory cell, but, due to its different connection relative to the supply lines LVDD1, LVDD2, stores different logic information and in particular complementary to that of cell C, at its nodes T, F,
    During the second phase Φ2 (FIG. 3B), the cell Ck is put into an operating mode of SRAM memory, insofar as the potentials applied respectively to the first supply line LVDD1 and to the second supply line LVDD2 are preferably equal, for example to VDD, and that a supply symmetry is obtained between the two sides of the cell allowing it to be made accessible both for reading and writing.
    The operating mode of cells C ,, Ck described above can allow the implementation of a memory device operating as a SRAM preloaded with ROM memory data thanks to an initialization sequence. It is then possible to read data stored by these cells Ci, Ck. This data is, for example, data relating to a boot program (“Boot” according to English terminology) required for example by a processor when starting or resetting a digital system.
    The supply lines LVDD1, LVDD2 make it possible in particular to initialize the first cell C, and to impose on it outside of its operating mode in conventional SRAM, and in particular prior to this operating mode in SRAM, a logic data item of pre- charge. The value of this initialization logic datum depends on the signals applied to the supply lines and for a given pair of signals, in the manner in which cell C is connected to the supply lines. The value of this logical datum imposed during the above-mentioned initialization sequence can thus be determined from the design of the device. The logical data imposed during the initialization sequence thus constitutes a ROM memory data. The set of ROM memory data or ROM memory code can then be determined by the designer of the device when he chooses, at the time of design, the manner in which each cell is arranged with respect to the supply lines. LVDD1 and LVDD2.
    An example of a particular embodiment of a circuit configured to apply couples of different potentials to the supply lines LVDD1 and LVDD2 and allow to pass from said first phase to said second phase mentioned above, is illustrated in FIG. 4.
    This circuit 40 makes it possible in particular to carry out a delayed power-up of one of the supply lines with respect to the other, in this example of the second supply line LVDD2 with respect to the supply line LVDD1. The circuit comprises a first portion 41 and a second portion 42 connected together and to a node receiving a supply voltage VDD. A switch element controlled by a control signal CMD1 is disposed between the first portion 41 and the first supply line LVDD1, while another switch element, controlled by a control signal CMD2, is arranged between the second portion 42 and the second LVDD2 supply line.
    The switching elements are for example transistors 44, 45, the respective gates of which receive the first control signal CMD1 and the second control signal CMD2 respectively. A change of state of the first control signal CMDl makes it possible to connect the first portion 41 to the first supply line LVDD1 (initialization of the preloaded values), the first supply line LVDD1 receiving the supply voltage VDD. Then (second phase), a change of state of the second control signal CMD2 delayed by a predetermined delay with respect to the first control signal CMDl makes it possible to connect the second portion 42 to the first supply line LVDD2, the first line d LVDD1 supply and the second supply line then both receiving the supply voltage VDD.
    A second example of circuit 50 making it possible to carry out an offset power-up between the two supply lines LVDD1, LVDD2 is illustrated in FIG. 5.
    Between one portion 51 of the circuit connected to a node capable of receiving a supply voltage VDD and the first supply line LVDD1, one or more buffers are provided (“buffer according to English terminology) also called separating amplifiers. Between another portion 54 able to receive the supply voltage VDD and the second supply line LVDD2, there are also one or more buffers 55a, 55b, 55c, 55d.
    The overall current gain of the buffer or buffers 55a, 55b, 55c, 55d provided between the portion 54 and the second supply line LVDD2 is preferably provided for, lower than the overall gain of the buffer or buffers 54a, 54b, 54c, 54d so inducing a delay in transmission of VDD on the LVDD2 supply line which is greater compared to the delay induced by the buffers 54a, 54b, 54c, 54d for transmitting VDD on the LVDD1 supply line.
    A third example of a circuit 60 allowing delayed power-up between the first supply line LVDD1 and the second supply line LVDD2 is shown schematically in FIG. 6.
    This circuit includes a first portion 61 connected to the first supply line LVDD1 and to a node capable of receiving the supply voltage VDD. A delay cell 65 is arranged between a second portion 62 of the circuit connected to said node and the second supply line LVDD2.
    The feed lines LVDD1 and LVDD2 are typically shared by cells of the same column of cells, that is to say cells which also typically share the same pair of bit lines BL T and BL F.
    To implement a polarization or supply dissociated from the TL T and TL F transistors, the LVDD1 and LVDD2 supply lines are typically provided in the form of separate metal lines which extend into a metallic level of interconnections situated above. transistors.
    The load transistors TL T and TL F are connected respectively to one of the two supply lines LVDD1 and LVDD2 and to the other of the two supply lines via conductive elements of the vias type.
    For a given memory cell, the placement of the vias making it possible to establish a connection between the transistors TL T and TL F respectively to one or the other of the supply lines LVDD1 or LVDD2 determines the value of the data that the we want to preload in this cell.
    Thus, the cell Ci described above has transistors TL T , TL F whose connections to the supply lines LVDD1, LVDD2 are arranged differently than those of the transistors TL T , TL F of the cell Ck which makes it possible to store data different between cell C, and cell Ck.
    FIGS. 7A-7D serve to illustrate a particular embodiment in which provision can be made for supply lines LVDD1, LVDD2 from a 2 nd metallic level also called “metal 2”. Different possible configurations of vias 71a, 71b, 72a, 72b, which extend between a first level of metal and the second level are given in these figures, a first load transistor being able to be connected either to the first supply line by via a via 71a or to the second supply line via a via 72a, while the other load transistor can be connected either to the first supply line via via via 71b or to the second supply line via via 72b.
    However, such an arrangement does not agree with all manufacturing technologies.
    Thus, another type of arrangement, more compatible with conventional manufacturing technologies, is proposed in the embodiment illustrated in FIGS. 8A-8B, with supply lines LVDD1, LVDD2 which extend in one level higher metallic level for example in a third level and a fourth metallic level comprising for example four metallic levels.
    In these figures a set of 8 elementary memory cells Ci m , C 2m , C 3m , C 4m , C 5m , C 6m C 7m , C 8m neighboring and belonging to different rows (horizontal rows) and belonging to the same column m of cells are shown.
    The cells Ci m , C 2m , C 3m , C 4m , C 5m , C 6m C 7m , C 8m are thus typically addressed by different word lines but are connected to the same pair of bit lines.
    In this example, a special arrangement of the connections to the LVDD1 and LVDD2 supply lines is also provided, each cell sharing a connection area 81 or 82 common to one of the LVDD1 and LVDD2 supply lines with a cell adjacent to a row. horizontal upper, and another common connection area 81 or 82 to a line among the supply lines LVDD1 and LVDD2 with another cell adjacent to a lower horizontal row. Such an arrangement makes it possible to reduce the bulk of the metal lines and associated vias.
    In this particular example, the cells Ci m , C 3m , C 5m , C 7m , of odd horizontal rows are provided with a connection zone 81 to the first supply line LVDD1 and with another connection zone 82 to the second LVDD2 line supply. The cubicles C 2m , C 4m , C 6m , C 8m , of even horizontal rows are provided with either two connection zones 81 or 82 to the same LVDD1 supply line or
    LVDD2, ie two connection zones 81, 82 connected to separate LVDD1, LVDD2 supply lines. With such an arrangement, the cells Ci m , C 3m , C 5m , C 7m , odd rows are able to be preloaded during the first phase resulting from the energization of the memory. The cells Ci m , C 3m , C 5m , C 7m are capable of forming a ROM memory whose data correspond to the values pre-loaded during the first phase mentioned above.
    As previously suggested, the data pre-loaded by cells Ci m , C 3m , C 5m , C 7m depend on the respective arrangements of the connections of their inverters to the supply line LVDD1 and to the other line of LVDD2 power supply.
    The cells Ci m , C 7m have similar arrangements with respect to each other of their connections 81, 82 respectively between their first inverter and the first supply line LVDD1 and between their second inverter and the second line of LVDD2 power supply. These cells Ci m , C 7m thus make it possible to store the same logical datum, for example a '1' at their first node T or a '0' at their complementary node F.
    C 3m , C 5m cells have arrangements of their connection areas 81, 82 different from that of cells Ci m , C 7m , but similar to each other. Thus their connections 82, 81 are this time respectively between their first inverter and the first supply line LVDD1 and between their second inverter and the second supply line LVDD2. These cells C 3m , C 5m allow the same logical data to be stored, for example a '0' at their first node T (or a '1' at their second complementary node F).
    In the example illustrated, the cells C 2m , C 6m are in a metastable state during the first phase of polarization of the lines LVDD1 and LVDD2 due to their connection to the same supply line, while the respective connections of the cells C 3m , C 7m for example impose a logical datum for example a '0' on the first node T of the cell C 3m and a logical datum for example a T on the first node T of the cell C 7m . The cells C 2m , C 4m , C 6m , C 8m , however, are not used as ROM memory cells during the operation where it is desired to access the data of the ROM memory. Because they share a common connection area with their respective neighboring cells, these cells C 2m , C 4m , C 6m , C 8m are therefore during the initialization sequence, in a state imposed by that of their neighboring cells cells C 2m , C 4m , C 6m , C 8m , and will not be read during a so-called "boot" phase of the circuit, during which read preloaded data.
    We therefore have a memory device of which one line is used (horizontal row) out of two during booting of the circuit. Alternatively, an arrangement can be provided in which only cells of even rows are accessed.
    Then, during the second phase, the LVDD1 and LVDD2 supply lines are set to the same potential and all the cells Ci m , C 3m , C 5m , Cym, C 2m , C 4m , C 6m , C 8m regain a polarization, with a balanced supply on both sides of each cell allowing them to function like a conventional SRAM.
    We therefore have a memory device of which we are likely to use all the lines (horizontal rows) once the ROM memory data preloaded during initialization have been read.
    FIG. 9A schematically illustrates a physical memory 90 which comprises a sector 92 of memory cells producing a RAM memory with one line in two preloaded with a boot code.
    The sector 92 is for example formed of a set of cells such as implemented according to the invention and having an arrangement of the type of that described above in particular in connection with FIGS. 8A-8B. Thus, in this sector 92, a horizontal row (line) of cells out of two, for example the even horizontal rows (or the odd horizontal rows), comprises preloaded cells which can be used as ROM memory during a phase known as priming then like, while the cells of the odd rows (or respectively the cells of the even rows) contain values imposed by the neighboring cells which are not used during the priming phase.
    In this FIG. 9A, the block 95 represents a set of virtual addresses seen from a processor or a central processing unit, (in English CPU for “central processing unit”) brought to exploit data from the physical memory 90 and belonging to a digital processing system.
    The processor can be brought, during a first memory access, corresponding for example to a system start-up or boot phase, to use or read program data, in particular a boot program (BOOT according to Anglo-Saxon terminology) stored in physical memory 90 and corresponding to cells of sector 92. Thus, one is likely to access, for example, cells Ci m , C 3m , C 5m , C 7m of FIGS. 8A-8B.
    The processor can then be caused, during a second memory access, to use RAM memory data, stored in sector 92. Cells of sector 92 of physical memory 90, which were read during the first access are thus can also be read and rewritten during the second access. If one refers to the example of arrangement described previously in connection with FIGS. 8A8B, the cells Ci m , C 3m , C 5m , C 7m can be read during access to the ROM memory then during 'access to RAM memory.
    In the embodiment of FIG. 9B, the physical memory comprises, in addition to the sector 92, another sector 94 composed of SRAM cells with conventional operation. Sector 94 is made up of cells which function like one of the SRAM cells of conventional type. Sector 94 is for example formed of cells having an arrangement of the type of cell C 2m described previously in connection with FIGS. 8A-8B, or else an arrangement of transistors which differs from that of the cells of FIGS. 1A-1B, 2A- 2B, in that its load transistors TL T , TL F are both connected to the same supply line, for example LVDD1 or LVVD2.
    The processor may be led, during a first memory access, corresponding for example to a system start-up or boot phase, to use or read program data, corresponding to cells of sector 92.
    The processor can then be brought, during a second memory access, to use RAM memory data, stored either in the sector 92 or in the sector 94.
    A differentiation between an access to the ROM memory and an access to the RAM memory is carried out by virtual address decoding upon reception of a read / write access request. This differentiation between access to the ROM memory and access to the RAM memory is carried out using a virtual address management module making it possible to convert a virtual address into a physical address.
    When the virtual address management module detects that access to the RAM memory is required, it applies a given type of operation to a virtual address to produce a physical address corresponding to one of the two sectors 92, 94. This type of operation can include an operation of subtracting an offset value (“offset” according to English terminology) from the virtual address.
    When an access to the ROM memory is required, a different type of operation is implemented, insofar as this does not occupy all the lines (horizontal rows) of sector 92. This type of operation can understanding an operation of subtracting another offset value as well as a shift, in order to produce a physical address corresponding for example only to an even or odd line of the physical memory 90.
    When it is odd horizontal lines or rows of physical memory which fulfill the function of ROM memory, a displacement of 1 to the left and an insertion of '1' can for example make it possible to produce a physical address corresponding to an odd line.
    As a variant, when the ROM memory is produced by even horizontal lines or rows, a displacement of 1 to the left and an insertion of '0' can make it possible, for example, to produce a physical address corresponding to an even line.
    Different examples of implementation of a module 100 for converting a virtual address into a physical address are given in FIGS. 10A-10C.
    These figures serve to illustrate respectively:
    a first case in which the module 100 is entirely dissociated from a support 98 on which the physical memory 90 is located,
    a second case in which the module 100 is partially located on the support 98 of the physical memory 90,
    a third case in which the module 100 is fully integrated on the same support 98 as the physical memory 90.
    In the second case, the memory support 98 can comprise a specific input signal to receive a ROM_MODE signal indicating a type of memory access made on the physical memory between an access to cells of this memory accessible in read only or to cells of this memory accessible in read and write.
    In the third case, the support 98 on which the memory is located can comprise a decoder 102, this decoder 102 then typically having mapping information linked to the virtual memory 95 seen from the processor.
    In all three cases, the module 100 is provided with a decoder 102 configured to use a virtual address "VirtualAddr" to emit a signal indicating the ROM_MODE type of memory access between an access relating to the ROM memory and a relative access to RAM memory. This indicator signal is different depending on whether access to the ROM memory or to the RAM memory is required. The decoder 102 can use “boot_size” data for this, linked to the size of the space reserved for the ROM memory 97.
    The decoder 102 is configured to transmit the signal indicating the type of memory access and to transmit the virtual address to an offset module 104 responsible for applying a type of operation called “offset” to the virtual address and producing in Consequently a physical address "PhysicalAddr" resulting from this operation. The type of operation performed by the shift module 104 is different depending on whether the memory access type indicator signal received by the shift module 104 indicates access to the ROM memory or access to the RAM memory.
    An example of the use of such a device in a digital system, comprising a processor, for example a graphics processor or GPU (for “Graphies Processing Unit”) or a digital signal processor (DSP for “Digital Signal Processor”) is the following :
    After switching on the digital system or starting the digital system, certain cells in sector 92, in particular the cells of even rows (or even the cells of odd rows), are preloaded by means of the first phase of polarization of the lines LVDD1, LVDD2, and the data of the ROM memory (sector 97 seen by the processor of the virtual memory 95) can be accessed by issuing requests comprising virtual addresses, typically presented incrementally starting with an address, called " boot_address ”, for example 0X0000.
    The decoder 102 identifies from the virtual address the type of memory access requested and in the present case detects access to the ROM memory. A signal for example through the input ROM_MODE maintained at the same potential indicates to the offset module 104 that an access to the ROM memory. This module 104 performs an operation on the virtual address so as to generate a physical address.
    Advantageously, the operation carried out is provided so as to produce a physical address giving access or corresponding only to odd rows of cells, or giving access or corresponding only to even rows of cells. The operation carried out is for example a bit shift to the left and addition of a '1' when the ROM memory cells are those of the odd rows in sector 92, or a bit shift to the left and an addition of '0 'when the ROM memory cells are those of the even rows of the sector 92.
    The data in the RAM memory (sector 99 seen by the processor) can then be accessed by starting with an address, located at boot_address + boot_size (boot_size corresponding to the size of ROM memory) corresponding for example to 0X2000.
    The decoder 102 identifies from the virtual address the type of memory access requested and in the present case detects access to the RAM memory. A signal for example by means of a change of polarity on the ROM_MODE input indicates to the module 104 an access to the RAM memory. This module 104 then performs an operation, for example by performing a subtraction operation of "boot_size" on the virtual address. This operation is therefore of a different type from that of the first phase. When accessing virtual sector 99, there is therefore no offset, just a subtraction.
    权利要求:
    Claims (16)
    [1" id="c-fr-0001]
    1. Memory device with:
    - a set of memory cells (Ci m , Cjm, C3m, C4m, Cs m , Cgm, C m, Csm, 0, Ck) each memory cell of said set comprising:
    - a first node (T) and a second node (F),
    - a first inverter and a second inverter cross-connected between said first node and said second node, the memory device further comprising:
    - a first supply line (LVDD1) connected to one of a first transistor of the first inverter and a second transistor of the second inverter,
    - a second supply line (LVDD2) connected to the other among said first transistor of the first inverter and said second transistor of the second inverter, the second supply line being separate from the first supply line, the memory device being equipped with a circuit (40, 50, 60) configured for during an initialization sequence:
    - during a first phase, apply a first pair of potentials (VDDlhigh, VDD2i ow ), respectively on the first supply line (LVDD1) and the second supply line (LVDD2), so as to impose on cells of said set, logic preload data, the respective values of which depend on the supply line among said first and second supply lines to which its first transistor and its second transistor are respectively connected, then
    - during a second phase apply a second pair of potentials (VDDlhigh, VDD2hi g h) respectively on said first supply line (LVDD1) and the second supply line (LVDD2), the second pair of potentials being different from the first pair potentials and planned so as to maintain these logical preload data and make the cells of said set accessible in read and write.
    [2" id="c-fr-0002]
    2. Memory device according to claim 1, at least a first cell (Ci m , Ci) of said assembly having its first inverter connected to the first supply line and its second inverter connected to the second supply line, at least other cell (Cjm, Ck) of said assembly having its two inverters connected to the same given supply line among said first supply line (LVDD1) and second supply line (LVDD2) or having its first inverter connected to the second line supply and its second inverter connected to the first supply line.
    [3" id="c-fr-0003]
    3. Memory device according to claim 2, in which a second cell (C ™) adjacent to the first cell (Ci m ) shares with the first cell a connection area common to one of said first supply line (LVDD1 ) or second supply line (LVDD2).
    [4" id="c-fr-0004]
    4. Memory device according to claim 3, wherein the second cell (C2m) has its two inverters connected to the same supply line through said first common connection area (82).
    [5" id="c-fr-0005]
    5. Memory device according to one of claims 3 or 4, in said set of cells comprises at least a third cell (Csm) located on the same column of cells as the first cell (Ci m ) and the second cell (Cjm) so that the second cell is located between the first cell and the third cell, the third cell having one of its inverters connected to the first supply line (LVDD1) and another of its inverters connected to the second supply line (LVDD2).
    [6" id="c-fr-0006]
    6. Memory device according to claim 5, in which said third cell (Cîm) is close to the second cell (C ™) and shares with the second cell a second common connection area (82), the second cell being disposed between the first cell and the third cell, the second common connection area being connected to the first supply line when the first common connection area is connected to the first supply line or, the second common connection area being connected to the second supply line when the first common connection area is connected to the second supply line.
    [7" id="c-fr-0007]
    7. A memory device according to claim 6, in which the first common connection area and the second common connection area are connected to the first supply line, said assembly being provided with at least a fourth cell arranged on the same column. cells as the first cell, the second cell and the third cell, the fourth cell having inverters connected to the second supply line.
    [8" id="c-fr-0008]
    8. Memory device according to one of claims 1 to 7, wherein said set of cells is a first set located in a first sector (92) of a matrix plane of cells, said matrix plane comprising a second sector (94) provided with a second set of memory cells, said cells of said second sector (94) being SRAM cells provided with inverters connected to the same supply line or receiving the same supply potential during the first phase and during the second phase of the initialization sequence.
    [9" id="c-fr-0009]
    9. Memory device according to one of claims 1 to 8, in which said assembly belongs to a matrix plane arranged in alternately even and odd columns and rows of cells,
    - in which the first memory cell (Clm) belongs to an odd horizontal row of cells and in which said other cell (C2m, Ck) of said set has its two inverters connected to the same supply line given among said first line of supply (LVDD1) and second supply line (LVDD2) and belongs to a pair of cell rows, or
    - in which the first memory cell (Clm) belongs to a paired horizontal row of cells, and in which said other cell (C2m, Ck) of said set has its two inverters connected to the same supply line given among said first line d supply (LVDD1) and second supply line (LVDD2) and belongs to an odd row of cells.
    [10" id="c-fr-0010]
    10. Memory device according to one of claims 1 to 9, further comprising a virtual memory address conversion module physical address memory, said conversion module (100) being provided with a shift module (104) configured for, following said initialization sequence:
    - detecting a signal indicating a first type of memory access relating to access to memory cells accessible in read-only mode of said set, and consequently applying a first type of operation to a virtual address in order to produce a physical address , then,
    - detecting a signal indicating a second type of memory access, relating to access to memory cells accessible for reading and writing said assembly, and to apply accordingly a second type of shift operation to a virtual address in order to to produce a physical address, the second type of operation being different from said first type of operation.
    [11" id="c-fr-0011]
    11. The memory device as claimed in claim 10, in which the first type of operation is provided so as to restrict access only to even horizontal rows among said horizontal rows of said set of cells or to restrict access only to rows horizontal odd among said horizontal rows of said set of cells, in which the second type of operation is capable of giving access to all of the horizontal rows of said set of cells.
    [12" id="c-fr-0012]
    12. Memory device according to claim 10 or 11, in which the conversion module comprises a decoder (102) configured for:
    - from a virtual address, produce a signal indicating a first type of relative memory access or a signal indicating a second type of memory access,
    transmitting this virtual address to the shift module, said set of cells, said shift module, and advantageously the decoder being arranged on the same support.
    [13" id="c-fr-0013]
    13. Memory device according to one of claims 1 to 12, in which the first phase is after powering up the memory device, said circuit being configured for:
    - during the first phase, apply the first pair of potentials by energizing the first supply line (LVDD1), in particular so as to apply a supply voltage VDD to it without supplying the second supply line (LVDD2), then, after a predetermined delay,
    - during the second phase apply the second pair of potentials by keeping the first supply line energized (LVDD1) while energizing the second supply line (LVDD2), preferably at the same supply voltage VDD.
    [14" id="c-fr-0014]
    14. Memory device according to claim 13, in which said circuit (40) comprises:
    - a first portion (41) and a second portion (42) of circuit each receiving a supply voltage VDD,
    - a first switch element (44) between the first portion and the first supply line (LVDD1), capable of alternately disconnecting and then connecting the first portion of the circuit to the first supply line (LVDD1) following a change of state of a first control signal (CMD1),
    - a second switching element (45) between the second portion and the second supply line (LVDD2), capable of alternately disconnecting and then connecting the second portion of the circuit to the second supply line (LVDD2) following a change of state of a second control signal (CMD2), the change of state of the second control signal (CIVID2) being delayed relative to the change of state of the first control signal (CMD1) according to said predetermined delay.
    [15" id="c-fr-0015]
    15. Memory device according to claim 13, in which said circuit (50) comprises:
    a first portion (51) and a second portion (52) each receiving a supply voltage VDD,
    5 - at least one first buffer (54a, 54b, 54c, 54d) between the first portion (51) and the first supply line (LVDD1),
    - at least one second buffer (55a, 55b, 55c, 55d) between the second portion (52) and the second supply line (LVDD2), said first buffer having a gain in current different from that of the second buffer.
    [16" id="c-fr-0016]
    16. Memory device according to claim 13, said circuit (60) comprising:
    a first portion (61) connected to the first supply line (LVDD1) and to a node (60) receiving a supply voltage VDD,
    - a second portion (62) connected to said node (60), at least one delay cell being disposed between the second portion (62) and the second supply line (LVDD2).
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    同族专利:
    公开号 | 公开日
    FR3083911B1|2021-01-22|
    EP3598451A1|2020-01-22|
    US20200020373A1|2020-01-16|
    US10861520B2|2020-12-08|
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    法律状态:
    2019-07-31| PLFP| Fee payment|Year of fee payment: 2 |
    2020-01-17| PLSC| Search report ready|Effective date: 20200117 |
    2020-07-31| PLFP| Fee payment|Year of fee payment: 3 |
    2021-07-29| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1856515A|FR3083911B1|2018-07-13|2018-07-13|RECONFIGURABLE SRAM / ROM MEMORY BY CONNECTIONS TO THE POWER SUPPLIES|FR1856515A| FR3083911B1|2018-07-13|2018-07-13|RECONFIGURABLE SRAM / ROM MEMORY BY CONNECTIONS TO THE POWER SUPPLIES|
    EP19186098.0A| EP3598451A1|2018-07-13|2019-07-12|Sram/rom memory reconfigurable by connections to power supplies|
    US16/510,235| US10861520B2|2018-07-13|2019-07-12|SRAM/ROM memory reconfigurable by supply connections|
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